Intel launch eclipsed by AMD’s post-Opteron plan

Chuck Moore's keynote blows Tom Yager away

Intel’s present drumbeat around the forthcoming Core Microarchitecture, multicore technology, and low power utilisation is intended to give it a major PR boost in the CPU battle with AMD. A fresh coat of paint on a retreat to a mobile architecture must have been the best Intel had to bring to the party, because when the party was held at the Spring Processor Forum, in San Jose last month, Intel just stayed away.

I can’t blame them. The keynote speech was given by Chuck Moore from AMD, who flattened the audience (me, at least) by breaking AMD’s months-long silence on the question: what comes after Opteron? Now we know. AMD’s major next-generation CPU will be no blast from the past. All the fantastic plans that AMD CTO Phil Hester related at the Fab 36 chip manufacturing plant grand opening in Dresden, Germany, are morphing into silicon at a far quicker pace than I expected.

Before I get to the amazing stuff, I’ll veer off into the merely remarkable. AMD is now shipping Revision F AMD64 CPUs, otherwise known as “those AMD processors with the hardware virtualisation support”. The specifications for AMD’s new dual-core Opteron include on-chip dual-channel DDR2 memory controllers, a 1,600MHz full-duplex Hypertransport I/O bus, a dedicated Direct Connect bus link between cores, 1MB of Level 2 cache per CPU, and an advanced power management solution that not only adds a deeper level of sleep to the CPU but chills the bus as well. I’ve told you that AMD had a long head-start over Intel on power efficiency.

Pardon me. Did I say Opteron? Damn. Those are the specs for AMD’s new notebook chip, the Turion 64 X2. The specs for AMD’s Athlon 64 FX-62 power desktop CPU are similar, and these beasts are rolling out of the Fab, as I type this. Rev F Opterons will be along presently.

Intel tried to cut AMD off at the knees on memory, accelerating its adoption of DDR2 and ramrodding a new standard, FB-DIMM (Fully Buffered DIMM), into the mix in a manner reminiscent of Intel’s prior fling with Rambus.

AMD is unfazed, because it has done the work needed to set itself up for DDR2, DDR3 and FB-DIMM. AMD’s manufacturing process will allow it to build DDR2, DDR3 and FB-DIMM CPUs simultaneously on the same line.

Intel, on the other hand, will build for FB-DIMM only, which will be bad news for customers if prices or supply come to strongly favour DDR3.

I’m delighted enough with what’s new now at AMD, but Chuck Moore laid out a mind-blowing future for AMD64 in his description of K8L, the architecture that will follow the current K8. K8L is (for starters) a four-core CPU. Yippee, right? Intel’s doing that, too. But AMD doesn’t do reactive engineering.

It’s obvious that AMD started work on K8L the day after Opteron shipped. K8L’s modular, on-board, dual-channel memory controllers and 1,600MHz Hypertransport bus are the sort of incremental improvements you might expect, but AMD is also taking up a set of big-iron features to carry x86 way past its Intel roots.

K8L will feature pooled Level 3 cache, a feature that x86 servers have needed from the start. The Hypertransport bus is getting a kick to Hypertransport 3, which is capable of handling 5.2 billion transactions per second. Remember, like K8, K8L will have multiple Hypertransport channels on each CPU. And you haven’t heard the half of it.

No wonder Dell did a deal with AMD to put AMD chips in its servers.

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