Every year brings a new spring IDF (Intel Developer Forum), but the 2007 IDF, held last month in Beijing, was special. The IDF is traditionally a low-key affair at which Intel’s developers teach other developers how to get the most out of the vendor’s hardware and tools. Intel always holds back some announcements in order to make a splash with new product news on the first day of the forum.
This year, IDF opening day was a show, Las Vegas meets Far East, with executives like CTO Justin Rattner, digital enterprise group general manager Pat Gelsinger and Eric Kim, GM of Intel’s Digital Home group, doing their best to whip the mostly native Beijing crowd into cheers and shouts with enthusiastic speeches interspersed with rappers and pyrotechnics. They announced Penryn, Intel’s next Core 2 Duo CPU and “the world’s first 45 nanometer product”, due late 2007, along with Nehalem, a CPU that will carry in a new microarchitecture in 2008, and Westmere, a Nehalem speed bump with a process shrink to 32 nanometers.
I was all set to write a great report on the IDF announcements when I stopped dead right at this sentence and asked myself, “Does anybody know what process shrink is? Does anybody really care?”
Chip chat should have no bearing on where you put your money, but Intel has made process size its marketing point of focus. If Intel’s going to sell nanometers, I figure it’s my duty to explain what it means, explain that it’s meaningless, and tell you the really important part of Intel’s announcements from Beijing.
Pencils ready? Good. A nanometer is one billionth of a metre, and each of Penryn’s transistors will measure 45 nanometers (nm) across. In contrast, back in 2000, most chip transistors were 180 nanometers wide, and they’ve gotten incrementally smaller to reach the current common size of 65 nm.
Intel’s prior shrinks were notable mostly for their more efficient use of real estate, which Intel predictably uses for more cores or larger cache. Smaller transistors also afford the advantage of switching at lower voltages, so they consume less power. In Intel’s case, however, its religion on performance per watt wasn’t derived primarily from process shrink. Rather, it was the result of falling back to a simpler microarchitecture. I’ll take lower power in any package, but it’s important to put process shrink and this whole nanometer business in perspective. It takes more than littler transistors to make a big difference in power consumption.
Why? If smaller transistors need less voltage to turn on, shouldn’t 45 nm be proportionally more efficient than 65 nm? Here’s where nanometers start to matter even less. Transistors leak; they never turn completely off. The current that slips through a transistor that’s supposed to be off does no work. It can’t be reclaimed. Instead, the power supply has to ratchet up to compensate for power lost to leakage. Leakage wastes power, generates heat, complicates system design, and reduces the top speed at which a chip can run. Smaller transistors leak as much as, if not more than, larger ones, and process shrink just gives you more leaks to plug.
At IDF, Intel brought to light the best weapon yet in the war on leakage: Hafnium. It’s a base element used for years in other electronic components, and to a transistor, Hafnium is a match made in heaven. Compared to silicon, Hafnium leaks far less. If it lives up to its research, its potential for low-power electronics is incredible. Intel is on a parallel track to Hafnium with the IBM/AMD/Sony process research partnership, but Intel deserves credit for getting Hafnium into production first, and for doing it while engineering a process shrink at the same time.
The point is, nanometers is not a worthy metric next to core chip design advances. Getting down to 45 nm only brought Intel to a Core 2 Duo with 12 MB of cache. Getting Hafnium to the x86 market before everybody else, and giving us a first taste of the fruits of the post-silicon era, deserves notice.